1. Field of the Invention
The present invention relates to a wiring substrate and a method for manufacturing the same. The wiring substrate of the present invention can be used in a liquid crystal display device, an organic or inorganic EL (electroluminescent) display device, a plasma display device, an electrochromic display device, or the like.
2. Description of the Background Art
On a TFT (thin film transistor) substrate used in a liquid crystal display device, or the like, a ring-shaped conductor pattern called “short ring” (hereinafter referred to as “SR”) is provided along the periphery of the substrate in order to prevent an electrostatic discharge (hereinafter referred to as “ESD”) damage while manufacturing the TFT substrate. Gate bus lines, storage capacitor lines, source bus lines, dummy lines, etc., are connected to SR. SR is typically removed in the scribing step or the beveling step after assembling the panel (see, for example, Japanese Laid-Open Patent Publication No. 8-234227).
FIG. 17 is a plan view schematically illustrating a TFT substrate being manufactured, after depositing a conductive film from which source bus lines are to be formed (hereinafter referred to also as “source film”) across the entire surface of the substrate. FIG. 18 is a cross-sectional view taken along line D-D′ of FIG. 17. A plurality of gate bus lines GL extending in the row direction, a plurality of storage capacitor lines Cs extending parallel to the gate bus lines GL, and gate terminals GT for electrically connecting the gate bus lines GL with the IC chip are formed on the substrate. In a case where the routing of the lines is difficult because of spatial limitations, a storage capacitor stem CsT connecting together a plurality of storage capacitor lines Cs may need to be provided between the gate bus lines GL and the gate terminals GT, as illustrated in FIG. 17, for example. Thus, there are gate metal lines connected to SR (e.g., the storage capacitor stem CsT, the gate bus lines GL and the dummy lines), and gate metal islands not connected to SR (e.g., COG (chip on glass) gate terminals and COG source terminals).
Moreover, a terminal VT for supplying a power supply voltage to the IC chip and other lines (not shown) for inputting driving signals to the IC chip are formed in an IC chip attachment area AA. A gate insulating film GI and a source film SF are successively deposited on these line patterns.
The gate insulating film GI includes a through hole GO near one end of each of the gate bus lines GL and the gate terminals GT. The charge that has been accumulated on the gate metal islands due to triboelectric charging, or the like, in the manufacturing process up to the deposition of the source film SF flows to the lines connected to SR via the through holes GO upon deposition of the source film SF. Thus, as the charge accumulated on the gate metal islands is released to SR, the lines on the substrate are all brought to an equipotential state. Note that the gate insulating film GI also includes the through holes GO in regions where the gate terminals GT overlap with the IC chip attachment area AA.
The deposited source film SF is then patterned to form source bus lines SL and connection patterns CP for connecting the gate bus lines GL with the gate terminals GT. FIG. 19 is a plan view schematically illustrating the TFT substrate after patterning the source film SF.
However, ESD occurs in a case where the distance between the through hole GO of a gate metal island and a gate metal line is shorter than the distance between the through hole GO of the gate island and the through hole GO of the gate metal line, e.g., in a case where the distance “a” between the through hole GO of the gate terminal GT and the storage capacitor stem CsT is shorter than the distance “b” between the through hole GO of the gate terminal GT and the through hole GO of the gate bus line GL. FIG. 20 is a cross-sectional view illustrating an occurrence of ESD. On the instant the source film SF is deposited, before the entire surface of the substrate is brought to an equipotential state, the potential difference (charge) created between the gate island and the gate metal line due to triboelectric charging, or the like, passes to a gate metal line portion that is closest to the gate island, thereby causing ESD.
FIG. 21 is a plan view illustrating the location where ESD occurs. In a case where ESD occurs in an area where a connection pattern CP for connecting the gate bus line GL with the gate terminal GT is formed, as illustrated in FIG. 21, a leak occurs between the gate bus line GL and the storage capacitor line Cs, thereby making the product defective.